Why HDI PCB Design Demands a Different CAD Approach
The shift from conventional through-hole boards to HDI PCB technology changes nearly every design assumption in CAD. HDI boards rely on microvias, via-in-pad, fine lines and spaces, and sequential lamination to achieve routing density and signal integrity that standard PCBs cannot reach. In a basic two-to-four layer design, a CAD tool primarily manages trace width, clearance, and through-hole via diameter. In an HDI design, the same tool must understand laser-drilled blind vias, buried vias, stacked and staggered microvia structures, and multiple sub-laminations that form the final board.
This complexity means the CAD environment must be configured before routing begins. A general-purpose default rule set will either block valid HDI structures or, worse, allow geometries that cannot be manufactured. For example, a blind via in HDI may have a laser drill diameter of 0.1 mm and land on a capture pad of 0.25 mm. If the CAD design rules still assume a 0.3 mm mechanical drill and a 0.6 mm pad, the design will be unnecessarily large and will not use the real advantage of HDI. Conversely, if the rules allow an aspect ratio above the fabricator’s capability, the board can fail in plating or thermal stress.
Modern CAD platforms aimed at advanced PCB design include dedicated HDI toolkits. These allow designers to define microvia types, span layers accurately, and check annular ring requirements for blind and buried structures. They also support true layer-pair drilling, where a laser via is formed from one layer to the next in a defined stack. Without this, a blind via may be incorrectly modeled as a through-hole and create shorts, misleading DRC results, or incorrect net connectivity.
In addition, HDI design often drives a different layout methodology. Because every square millimeter matters, designers place high-pin-count BGAs, impedance-controlled differential pairs, and decoupling capacitors in tight clusters. The CAD tool must allow fanout and escape routing with microvias, test point reduction, and pad-only vias. It should also support design rules that differentiate between outer-layer and inner-layer structures, since HDI boards frequently use thinner dielectrics and lower copper weights. When set up correctly, CAD becomes not just a drafting tool but a manufacturability engine that catches electrical and physical issues before fabrication.
Configuring Stackups, Microvias, and Design Rules for HDI
A successful HDI CAD workflow starts in the layer stackup manager. Unlike simple boards, HDI stackups often use sequential lamination, also called build-up or BUM. The CAD model should reflect the true construction sequence: a core with buried vias, then prepreg and copper foil added, laser-drilled microvias formed, plated, and then additional build-up layers applied. If the CAD stackup uses a single “all layers” model, it cannot correctly represent stacked microvias or buried vias that do not span the entire board. This leads to false DRC passes and manufacturability problems.
Create separate drill pairs for each build-up stage. For example, a 3+N+3 HDI board has three layers on top of the core and three on the bottom. The CAD tool should show drill pairs from layer 1 to 2, 2 to 3, and 3 to the underlying core, plus the mirrored pairs on the bottom. This allows you to place blind microvias exactly where they belong. The same setup enables stacked microvia structures, where vias are aligned from one build-up layer to the next, or staggered structures, where they are offset to reduce stress and improve reliability. Selecting between stacked and staggered affects routing density, thermal performance, and cost, so CAD support for both is crucial.
Next, replace default via definitions with HDI-specific via types. A via-in-pad strategy is common for BGA escape under fine pitch parts. In CAD, this means the via is placed directly in the component land pad, often filled and capped or plated over. The design rules must allow the via pad to share a component pad without flagging a short. The software should also handle microvia aspect ratio constraints, typically 1:1 or lower for laser drilling. If a 0.1 mm via needs to span a 0.08 mm dielectric, the rule can pass; if it tries to span 0.15 mm, the DRC should flag it.
Set trace width and spacing rules to match HDI process capabilities. It is common to use 75 µm (3 mil) lines and spaces or even 50 µm (2 mil) on advanced HDI. However, finer geometries affect copper thickness, etch factor, and impedance tolerance. CAD rules should include minimum air gap, solder mask dam width, and pad-to-trace clearance for via-in-pad designs. Impedance-controlled nets such as PCIe, USB, or DDR need layer-specific width calculations based on the chosen HDI materials. Use the CAD field solver or an integrated impedance calculator to lock these values before routing.
Finally, save a reusable HDI rule set or template. Many design teams work on automotive radar modules, medical wearables, and telecom backhaul boards that share similar HDI structures. A well-tested template reduces setup time and prevents repeated mistakes. It also helps when collaborating with fabricators because the CAD data accurately signals the intended microvia structure, stackup, and manufacturing class.
Routing, Verification, and DFM for HDI CAD Workflows
With the stackup and rules prepared, routing in HDI CAD becomes a balance of density, signal integrity, and manufacturability. High-density escape routing usually starts with the processor or FPGA BGA. The CAD tool should support automated fanout with microvias, placing a via-in-pad for each ground or power ball and then routing signals outward on lower layers. Use blind via escape patterns to keep outer-layer traces short and to free space for decoupling capacitors. For fine-pitch BGAs with 0.5 mm or 0.4 mm ball spacing, a single microvia in each pad may be the only practical escape path. The CAD tool must correctly angle the traces and maintain the required neck-down clearance without violating annular ring rules.
Signal integrity tools inside the CAD environment become more important in HDI because the thin dielectrics and tight spacing increase coupling. Differential pairs for high-speed serial links need controlled spacing, matched length, and consistent return paths. Use the CAD constraint manager to assign differential-pair rules, phase tolerance, and maximum uncoupled length. For very dense HDI boards, consider buried and blind via stitching around sensitive nets to create shield fences. The CAD tool can also run crosstalk simulations and layer transition checks to confirm that via transitions do not create unwanted stubs. In HDI, microvias have very short stubs, which is a major electrical advantage over through-hole vias.
After routing, run a full design rule check, but do not rely on generic DRC alone. HDI-specific checks should include microvia span layers, solder mask clearance on via-in-pad, copper-to-edge spacing, and minimum annular ring on laser vias. Use the CAD tool’s 3D view to inspect dense BGA areas and stacked via structures. This helps catch missing capping or incorrect drill pairs that are not obvious in 2D. Also verify that the design matches the fabricator’s process window. Many manufacturers publish HDI design guidelines covering laser drill size, dielectric thickness, via fill type, and pad-to-via ratio. Import or manually enter these as custom DRC rules.
One of the most effective ways to avoid respins is to combine the CAD design flow with a fabricator-ready checklist. A structured guide on How to Design for HDI PCB Using CAD Software can help teams align material selection, via structures, and output files before the board moves to production. This is especially useful for automotive camera modules, high-density medical sensors, and aerospace communication boards where reliability and miniaturization must coexist.
Finally, generate manufacturing outputs directly from the CAD tool. Include ODB++ or IPC-2581 data so the fabricator receives the true stackup and netlist, not just Gerber files. Add a detailed fabrication drawing that notes sequential lamination steps, microvia fill and cap requirements, impedance test coupons, and any back-drilling or buried via details. When the CAD data is complete and HDI-aware, the manufacturing team can review the board quickly, suggest minor adjustments, and keep the project moving toward a reliable, high-yield result.
Istanbul-born, Berlin-based polyglot (Turkish, German, Japanese) with a background in aerospace engineering. Aysel writes with equal zeal about space tourism, slow fashion, and Anatolian cuisine. Off duty, she’s building a DIY telescope and crocheting plush black holes for friends’ kids.